TPIC6B595N Counter Shift Registers

• Low RDS_(on),5 Ω (Typical)
• Avalanche Energy, 30 mJ
• Eight Power DMOS Transistor Outputs of 150-mA Continuous Current
• Output Clamp Voltage, 50 V
• Devices are Cascadable
• Low-Power Consumption

TPIC6B595N Counter Shift Registers device is a monolithic, high-voltage and medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through the shift and storage register on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR\) is high. SRCLR\ is low, the input shift register is cleared. When output enables (G\) is held high, all data in the output buffers is held low and all drain outputs are off.

When G\ is held low, data from the storage register is transparent to the output buffers. If and when data in the output buffers is low, the DMOS-transistor outputs are off. If data is high, the DMOS transistor outputs have the sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at T_C = 25°C. The current limit decreases as the junction temperature increases for

additional device protection.

The TPIC6B595 is characterized for operation over the operating case temperature range of −40°C to 125°C. For all available packages, see the orderable addendum at the end of the datasheet.

What is a Shift register?

A shift register is a type of digital circuit using a cascade of flip flops. Where the output of one flip-flop is connected to the input of the next. They share a single clock signal, which causes the data stored in the system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this form, they were used as a form of computer memory. In this role, they are very similar to the earlier delay line memory systems and were widely used in the late 1960s and early 1970s to replace that form of memory.

Reference

Arduino Tutorial 43:

Binary Counter with 74HC595 Serial to Parallel Shift Register

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